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Called the &# 8216;PolarFire SoC', the architecture enables real-time deterministic asymmetric multiprocessing on Linux platforms in a multi-core coherent CPU cluster, according to the firm, which worked with Risc-V specialist SiFive. to create devices<\/p>\n
Real-time operations are included for security-critical, system management, and trusted execution environments.<\/p>\n
This is achieved by disabling CPU branch predictors, converting level 1 cache to tightly integrated memory, ensuring that all cores are aligned with the memory subsystem and share the aligned memory for message passing.<\/p>\n
Four cores execute the RV64GC instruction set. To monitor them, there is a fifth 64-bit Risc-V, which this time executes the RV64IMAC instruction set. All five can work in concert.<\/p>\n
Risc-V versions inherit security features from existing PolarFire FPGAs, including: DPA-resistant bitstream programming, tamper protection, cryptographic tied supply chain assurance, physical fault-cloning functionality, true random number generator, and side-channel resistant crypto - co-processor.<\/p>\n
In addition, according to Microchip, the processors will have secure boot (128 Kbytes of boot flash memory), physical memory protection and, on all types of memory: one-bit error correction and two-bit error detection. The firm also claims protection against Specter and Meltdown.<\/p>\n
Before the chips are available, Antmicro's open source Renode framework can be used, and Microchip has created a 'HiFive Unleashed Expansion Board' to work alongside the HiFive 'Unleashed Development Board' - Microchip has named both boards together: MPFS-DEV-KIT.<\/p>\n
For existing PolarFire FPGAs, Microchip has 'Mi-V' 32-bit Risc-V software cores that execute the RV32I (integer) instruction set, some with 'M' (multiply\/divide), 'A' (atomic instruction), or 'F ' (single precision floating point).<\/p>\n
Microchip presented at 'Getting Started with RISC-V' last week in London.<\/p>\n